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Nickname: asicwithankit     Articles(7)    Visits(39527)    Comments(5)    Votes(24)    RSS
ASIC with Ankit covers ASIC design verification, languages and methodology. The author, Ankit Gopani, works as a Lead Design Verification Engineer with SmartPlay Inc. He has 9 years of industry experience in ASIC design verification and executed several Verification projects.
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Posted: 09:53:54 PM, 13/03/2013

What are the major factor which could trigger re-spin?

   

Dear Readers,

I have been hearing on re-spins of chips. Many companies have gone through this painful phase because of several reason/defects. Nobody likes re-spin for chip as it is expensive and time consuming! Companies have a fear to loose time to market for their products because of this reason.
 
Let us understand the various factors which could cause re-spin for chips. If you ask industry experts or Semiconductor veterans they could share their experience. I have been discussing this topic with couple of people and have concluded few factors which could cause re-spin.
  1. Firmware Issues
  2. Power Issues
  3. Mixed-Signal Interface related Issues
  4. Race Condition Issues
  5. Clocking domain Issues
  6. Functional Issue etc...
From the experience and discussion it looks like most of the time Function Issues/defects have triggered a re-spin for the Chips. When we talk about functional issues, attention comes to our mind is for functional logic verification part. Considering complexities in the ASICs companies have started investing time and money for the functional verification part of the Chips to reduce the chances of re-spin.
 
To reduce the chances of re-spin for chips, people have started using various precautions like
 
1. A reusable and scalable verification
2. More effective block (IP) level verification.
3. Verification reuse from block level to System level
4. Constraint Random Verification approach
5. Architecture of test bench using reusable methodologies

Random functional verification is giving us a enough confidence on functional defects. Random verification generates corner scenarios, stress testing on functional scenarios and logical permutation for configuration.

 
Random verification just gives us a confidence on functional defects but not giving us confirmation that Chip will not have to go through re-spin because of any of the functional issue.
 
Share your experience on Chip re-spin.
 
Happy Reading-Sharing,
ASIC With Ankit
Views(1694) Comments(2)
Total [3] users voted     
[Last update: 09:53:54 PM, 13/03/2013]

Visitor:

Visitor 10:41:00 PM, 19/03/2013
Comment:

Quality of test plan give us more confidence irrespective of methodology, in my point of view beacause we will ensure it by coverage.

 

Visitor:

Visitor 10:51:18 PM, 19/03/2013
Comment:

Nice article, i would like to add one more point, Quality of test plan give us more confidence irrespective of methodology following because we can ensure bt coverage, Quality of ur test plan always proportional to Quality of product.

Regards,

Narasimha

 

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